1. Field of the Invention
The present invention relates to a semiconductor device including three or more wiring layers.
2. Description of Related Art
According to the growing digitization of our society, demand for high-performance and high-speed semiconductor devices is increasing. In order to meet the demand, large-scale integration of the semiconductor devices has been proceeding while the multi-layering and miniaturization of wiring are involved in. In recent years, in order to reduce parasitic capacitance derived from the miniaturization of the wiring for the purpose of enhancing the speed of the semiconductor devices, dielectric material having a lower dielectric constant (low-k material) has been used for an interlayer insulating film in place of conventional dielectric oxide material such as silicon oxide and silicon nitride.    Patent Document 1: Japanese Unexamined Patent Publication No. 2003-243401    Patent Document 2: Japanese Unexamined Patent Publication No. 2004-153015